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gensoc: missing self.

This commit is contained in:
Robert Jordens 2015-02-26 20:19:39 -07:00 committed by Sebastien Bourdeauducq
parent a3909bb5e2
commit c9ed38dec8
1 changed files with 1 additions and 1 deletions
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2
misoclib/gensoc/__init__.py
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@ -193,7 +193,7 @@ class SDRAMSoC(GenSoC):
self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), sdramcon.bus)
elif (sdram_width < 32):
self.submodules.dc = wishbone.DownConverter(32, sdram_width)
self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus)
self.submodules.intercon = wishbone.InterconnectPointToPoint(self.dc.wishbone_o, sdramcon.bus)
self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.dc.wishbone_i)
else:
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))