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soc/integration/soc_core: Add SRAM/ROM burst cycles support switch

This commit is contained in:
Rafal Kolucki 2022-04-05 14:15:26 +02:00
parent 54f897f446
commit ca78f799e1
2 changed files with 19 additions and 11 deletions
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8
litex/soc/integration/soc.py
View File

@ -837,7 +837,7 @@ class SoC(Module):
colorer("added", color="green"))) colorer("added", color="green")))
setattr(self.submodules, name, SoCController(**kwargs)) setattr(self.submodules, name, SoCController(**kwargs))
def add_ram(self, name, origin, size, contents=[], mode="rw"): def add_ram(self, name, origin, size, contents=[], mode="rw", burst=False):
ram_cls = { ram_cls = {
"wishbone": wishbone.SRAM, "wishbone": wishbone.SRAM,
"axi-lite": axi.AXILiteSRAM, "axi-lite": axi.AXILiteSRAM,
@ -847,7 +847,7 @@ class SoC(Module):
"axi-lite": axi.AXILiteInterface, "axi-lite": axi.AXILiteInterface,
}[self.bus.standard] }[self.bus.standard]
ram_bus = interface_cls(data_width=self.bus.data_width) ram_bus = interface_cls(data_width=self.bus.data_width)
ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r")) ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"), burst=burst)
self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode)) self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
self.check_if_exists(name) self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format( self.logger.info("RAM {} {} {}.".format(
@ -858,8 +858,8 @@ class SoC(Module):
if contents != []: if contents != []:
self.add_config(f"{name}_INIT", 1) self.add_config(f"{name}_INIT", 1)
def add_rom(self, name, origin, size, contents=[], mode="r"): def add_rom(self, name, origin, size, contents=[], mode="r", burst=False):
self.add_ram(name, origin, size, contents, mode=mode) self.add_ram(name, origin, size, contents, mode=mode, burst=burst)
def init_rom(self, name, contents=[], auto_size=True): def init_rom(self, name, contents=[], auto_size=True):
self.logger.info("Initializing ROM {} with contents (Size: {}).".format( self.logger.info("Initializing ROM {} with contents (Size: {}).".format(

20
litex/soc/integration/soc_core.py
View File

@ -78,14 +78,17 @@ class SoCCore(LiteXSoC):
integrated_rom_size = 0, integrated_rom_size = 0,
integrated_rom_mode = "r", integrated_rom_mode = "r",
integrated_rom_init = [], integrated_rom_init = [],
integrated_rom_burst = False,
# SRAM parameters # SRAM parameters
integrated_sram_size = 0x2000, integrated_sram_size = 0x2000,
integrated_sram_init = [], integrated_sram_init = [],
integrated_sram_burst = False,
# MAIN_RAM parameters # MAIN_RAM parameters
integrated_main_ram_size = 0, integrated_main_ram_size = 0,
integrated_main_ram_init = [], integrated_main_ram_init = [],
integrated_main_ram_burst = False,
# CSR parameters # CSR parameters
csr_data_width = 32, csr_data_width = 32,
@ -198,7 +201,8 @@ class SoCCore(LiteXSoC):
origin = self.cpu.reset_address, origin = self.cpu.reset_address,
size = integrated_rom_size, size = integrated_rom_size,
contents = integrated_rom_init, contents = integrated_rom_init,
mode = integrated_rom_mode mode = integrated_rom_mode,
burst = integrated_rom_burst
) )
# Add integrated SRAM # Add integrated SRAM
@ -206,6 +210,7 @@ class SoCCore(LiteXSoC):
self.add_ram("sram", self.add_ram("sram",
origin = self.mem_map["sram"], origin = self.mem_map["sram"],
size = integrated_sram_size, size = integrated_sram_size,
burst = integrated_sram_burst
) )
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available) # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
@ -214,6 +219,7 @@ class SoCCore(LiteXSoC):
origin = self.mem_map["main_ram"], origin = self.mem_map["main_ram"],
size = integrated_main_ram_size, size = integrated_main_ram_size,
contents = integrated_main_ram_init, contents = integrated_main_ram_init,
burst = integrated_main_ram_burst,
) )
# Add Identifier # Add Identifier
@ -312,11 +318,13 @@ def soc_core_args(parser):
soc_group.add_argument("--no-ctrl", action="store_true", help="Disable Controller.") soc_group.add_argument("--no-ctrl", action="store_true", help="Disable Controller.")
# ROM parameters # ROM parameters
soc_group.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (Automatically resized to BIOS size when smaller).") soc_group.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (Automatically resized to BIOS size when smaller).")
soc_group.add_argument("--integrated-rom-init", default=None, type=str, help="Integrated ROM binary initialization file (override the BIOS when specified).") soc_group.add_argument("--integrated-rom-init", default=None, type=str, help="Integrated ROM binary initialization file (override the BIOS when specified).")
soc_group.add_argument("--integrated-rom-burst", default=False, action="store_true", help="Enable burst cycles support in integrated ROM (works only for Wishbone interconnect).")
# SRAM parameters # SRAM parameters
soc_group.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM.") soc_group.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM.")
soc_group.add_argument("--integrated-sram-burst", default=False, action="store_true", help="Enable burst cycles support in integrated ROM (works only for Wishbone interconnect).")
# MAIN_RAM parameters # MAIN_RAM parameters
soc_group.add_argument("--integrated-main-ram-size", default=None, type=auto_int, help="size/enable the integrated main RAM.") soc_group.add_argument("--integrated-main-ram-size", default=None, type=auto_int, help="size/enable the integrated main RAM.")