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Merge pull request #328 from betrusted-io/precise_clocks 

add the possibility for a "precise" clock solution
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enjoy-digital 2020-01-01 13:20:15 +01:00 committed by GitHub
parent 9336fe1139 219bb7f294
commit caacc41103
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litex/soc/cores/clock.py
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@ -74,7 +74,7 @@ class XilinxClocking(Module, AutoCSR):
valid = False valid = False
for d in range(*self.clkout_divide_range): for d in range(*self.clkout_divide_range):
clk_freq = vco_freq/d clk_freq = vco_freq/d
if abs(clk_freq - f) < f*m: if abs(clk_freq - f) <= f*m:
config["clkout{}_freq".format(n)] = clk_freq config["clkout{}_freq".format(n)] = clk_freq
config["clkout{}_divide".format(n)] = d config["clkout{}_divide".format(n)] = d
config["clkout{}_phase".format(n)] = p config["clkout{}_phase".format(n)] = p