Merge pull request #328 from betrusted-io/precise_clocks

add the possibility for a "precise" clock solution
2020-01-01 13:20:15 +01:00 · 2020-01-01 13:20:15 +01:00 · caacc41103
parent 9336fe1139 219bb7f294
commit caacc41103
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@ -74,7 +74,7 @@ class XilinxClocking(Module, AutoCSR):
                        valid = False
                        for d in range(*self.clkout_divide_range):
                            clk_freq = vco_freq/d
-                            if abs(clk_freq - f) < f*m:
+                            if abs(clk_freq - f) <= f*m:
                                config["clkout{}_freq".format(n)]   = clk_freq
                                config["clkout{}_divide".format(n)] = d
                                config["clkout{}_phase".format(n)]  = p