Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

cores/uart/RS232ClkPhaseAccum: Avoid reset on phase signal, improve timings/resources on iCE40.

Browse source
This commit is contained in:
Florent Kermarrec 2021-06-20 14:33:25 +02:00
parent 4c8184fbb6
commit d6f24f2f68
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/soc/cores/uart.py
View file

@ -46,7 +46,7 @@ class RS232ClkPhaseAccum(Module):
# # #
phase = Signal(32)
phase = Signal(32, reset_less=True)
self.sync += Cat(phase, self.tick).eq(tuning_word if mode == "tx" else 2**31)
self.sync += If(self.enable, Cat(phase, self.tick).eq(phase + tuning_word))