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soc/cores/clock/intel_common: cleanup

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Thomas Watson 2022-10-01 12:28:32 -05:00
parent 3836e8a36c
commit d89d6dfd0a
1 changed files with 5 additions and 5 deletions
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10
litex/soc/cores/clock/intel_common.py
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@ -115,10 +115,10 @@ class IntelClocking(Module, AutoCSR):
o_LOCKED = self.locked, o_LOCKED = self.locked,
) )
for n, (clk, f, p, m) in sorted(self.clkouts.items()): for n, (clk, f, p, m) in sorted(self.clkouts.items()):
clk_phase_ps = int((1e12/config["clk{}_freq".format(n)])*config["clk{}_phase".format(n)]/360) clk_phase_ps = int((1e12/config[f"clk{n}_freq"])*config[f"clk{n}_phase"]/360)
self.params["p_CLK{}_DIVIDE_BY".format(n)] = config["clk{}_divide".format(n)] self.params[f"p_CLK{n}_DIVIDE_BY"] = config[f"clk{n}_divide"]
self.params["p_CLK{}_DUTY_CYCLE".format(n)] = 50 self.params[f"p_CLK{n}_DUTY_CYCLE"] = 50
self.params["p_CLK{}_MULTIPLY_BY".format(n)] = config["m"] self.params[f"p_CLK{n}_MULTIPLY_BY"] = config["m"]
self.params["p_CLK{}_PHASE_SHIFT".format(n)] = clk_phase_ps self.params[f"p_CLK{n}_PHASE_SHIFT"] = clk_phase_ps
self.comb += clk.eq(clks[n]) self.comb += clk.eq(clks[n])
self.specials += Instance("ALTPLL", **self.params) self.specials += Instance("ALTPLL", **self.params)