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soc/cores/pwm: add clock_domain support

This commit is contained in:
Florent Kermarrec 2019-12-16 11:13:10 +01:00
parent 9da28c4ea5
commit da3a178bc6
1 changed files with 11 additions and 8 deletions
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19
litex/soc/cores/pwm.py
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@ -16,7 +16,7 @@ class PWM(Module, AutoCSR):
Pulse Width Modulation can be useful for various purposes: dim leds, regulate a fan, control Pulse Width Modulation can be useful for various purposes: dim leds, regulate a fan, control
an oscillator. Software can configure the PWM width and period and enable/disable it. an oscillator. Software can configure the PWM width and period and enable/disable it.
""" """
def __init__(self, pwm=None, with_csr=True): def __init__(self, pwm=None, clock_domain="sys", with_csr=True):
if pwm is None: if pwm is None:
self.pwm = pwm = Signal() self.pwm = pwm = Signal()
self.enable = Signal() self.enable = Signal()
@ -27,7 +27,8 @@ class PWM(Module, AutoCSR):
counter = Signal(32) counter = Signal(32)
self.sync += [ sync = getattr(self.sync, clock_domain)
sync += [
If(self.enable, If(self.enable,
counter.eq(counter + 1), counter.eq(counter + 1),
If(counter < self.width, If(counter < self.width,
@ -45,15 +46,17 @@ class PWM(Module, AutoCSR):
] ]
if with_csr: if with_csr:
self.add_csr() self.add_csr(clock_domain)
def add_csr(self): def add_csr(self, clock_domain):
self._enable = CSRStorage() self._enable = CSRStorage()
self._width = CSRStorage(32) self._width = CSRStorage(32)
self._period = CSRStorage(32) self._period = CSRStorage(32)
self.comb += [ n = 0 if clock_domain == "sys" else 2
self.enable.eq(self._enable.storage), print(n)
self.width.eq(self._width.storage), self.specials += [
self.period.eq(self._period.storage) MultiReg(self._enable.storage, self.enable, n=n),
MultiReg(self._width.storage, self.width, n=n),
MultiReg(self._period.storage, self.period, n=n),
] ]