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tools/litex_sim/add_sdram: origin no longer required.

This commit is contained in:
Florent Kermarrec 2022-03-17 16:47:02 +01:00
parent 05724d9fea
commit dd7709ed6f
1 changed files with 0 additions and 1 deletions
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litex/tools/litex_sim.py
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@ -187,7 +187,6 @@ class SimSoC(SoCCore):
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = sdram_module, module = sdram_module,
origin = self.mem_map["main_ram"],
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = False l2_cache_reverse = False