tools/litex_sim/add_sdram: origin no longer required.

2022-03-17 16:47:02 +01:00 · 2022-03-17 16:47:02 +01:00 · dd7709ed6f
parent 05724d9fea
commit dd7709ed6f
1 changed files with 0 additions and 1 deletions
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@ -187,7 +187,6 @@ class SimSoC(SoCCore):
            self.add_sdram("sdram",
                phy                     = self.sdrphy,
                module                  = sdram_module,
-                origin                  = self.mem_map["main_ram"],
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = False