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soc/cores/spi_flash: fix with_bitbang=False compilation.

This commit is contained in:
Florent Kermarrec 2020-10-07 19:32:10 +02:00
parent 375b6f2dc7
commit e4fe0d9ef4
1 changed files with 3 additions and 2 deletions
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5
litex/soc/cores/spi_flash.py
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@ -133,8 +133,9 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
self.specials.dq1 = Tristate(pads.dq[1], o=dq.o[1], i=dq.i[1], oe=dq.oe) self.specials.dq1 = Tristate(pads.dq[1], o=dq.o[1], i=dq.i[1], oe=dq.oe)
if spi_width > 2: if spi_width > 2:
# Keep DQ2,DQ3 as outputs during bitbang, this ensures they activate ~WP or ~HOLD functions # Keep DQ2,DQ3 as outputs during bitbang, this ensures they activate ~WP or ~HOLD functions
self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=(dq.oe | self.bitbang_en.storage)) bitbang_en = 0 if not with_bitbang else self.bitbang_en.storage
self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=(dq.oe | self.bitbang_en.storage)) self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=(dq.oe | bitbang_en))
self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=(dq.oe | bitbang_en))
sr = Signal(max(cmd_width, addr_width, wbone_width)) sr = Signal(max(cmd_width, addr_width, wbone_width))
if endianness == "big": if endianness == "big":