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Merge pull request #1543 from stone3311/master 

build/altera: Fix IP integration
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enjoy-digital 2022-12-23 19:50:19 +01:00 committed by GitHub
parent 5dd1bb5fdb 5307b5e3f2
commit e8322587a0
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1 changed files with 2 additions and 3 deletions
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litex/build/altera/quartus.py
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@ -138,10 +138,9 @@ class AlteraQuartusToolchain(GenericToolchain):
if fpath not in platform.verilog_include_paths:
platform.verilog_include_paths.append(fpath)
# Add ips
# Add IPs
for filename in self.platform.ips:
tpl = "set_global_assignment -name QSYS_FILE {filename}"
qsf.append(tpl.replace(filename=filename.replace("\\", "/")))
qsf.append("set_global_assignment -name QSYS_FILE " + filename.replace("\\", "/"))
# Add include paths
for path in self.platform.verilog_include_paths: