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boards: keep in sync with LiteX-boards

This commit is contained in:
Florent Kermarrec 2020-02-27 11:18:14 +01:00
parent 935e4effd2
commit eab5161d47
6 changed files with 87 additions and 76 deletions
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6
litex/boards/platforms/kc705.py
View File

@ -120,7 +120,8 @@ _io = [
Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")),
Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
Subsignal("dm", Pins(
"Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",
@ -155,7 +156,8 @@ _io = [
Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AC12 AE8"), IOStandard("SSTL15")),
Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
Subsignal("dm", Pins(
"Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",

24
litex/boards/platforms/kcu105.py
View File

@ -112,29 +112,31 @@ _io = [
Subsignal("we_n", Pins("AD16"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cs_n", Pins("AL19"), IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("AH14"), IOStandard("SSTL12_DCI")),
Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")),
Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")),
Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")),
#Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")),
#Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")),
#Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"),
IOStandard("POD12_DCI")),
Subsignal("dq", Pins(
"AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20",
"AJ24 AG24 AJ23 AF23 AH23 AF24 AH22 AG25",
"AL22 AL25 AM20 AK23 AK22 AL24 AL20 AL23",
"AM24 AN23 AN24 AP23 AP25 AN22 AP24 AM22",
"AH28 AK26 AK28 AM27 AJ28 AH27 AK27 AM26",
"AL30 AP29 AM30 AN28 AL29 AP28 AM29 AN27",
"AH31 AH32 AJ34 AK31 AJ31 AJ30 AH34 AK32",
"AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32",
),
IOStandard("POD12_DCI")),
"AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32"),
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"),
IOStandard("DIFF_POD12")),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"),
IOStandard("DIFF_POD12")),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("clk_p", Pins("AE16"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_n", Pins("AE15"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cke", Pins("AD15"), IOStandard("SSTL12_DCI")),

2
litex/boards/targets/kcu105.py
View File

@ -124,7 +124,7 @@ class EthernetSoC(BaseSoC):
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex/boards/targets/nexys_video.py
View File

@ -89,8 +89,8 @@ class EthernetSoC(BaseSoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

41
litex/boards/targets/ulx3s.py
View File

@ -5,17 +5,18 @@
# License: BSD
import argparse
import sys
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import ulx3s
from litex_boards.platforms import ulx3s
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT48LC16M16
from litedram import modules as litedram_modules
from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
@ -27,33 +28,32 @@ class _CRG(Module):
# # #
# clk / rst
# Clk / Rst
clk25 = platform.request("clk25")
rst = platform.request("rst")
platform.add_period_constraint(clk25, 40.0)
platform.add_period_constraint(clk25, 1e9/25e6)
# pll
# PLL
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(rst)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
# sdram clock
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# Stop ESP32 from resetting FPGA
wifi_gpio0 = platform.request("wifi_gpio0")
self.comb += wifi_gpio0.eq(1)
# Prevent ESP32 from resetting FPGA
self.comb += platform.request("wifi_gpio0").eq(1)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, device="LFE5U-45F", toolchain="diamond", **kwargs):
platform = ulx3s.Platform(device=device, toolchain=toolchain)
sys_clk_freq = int(50e6)
def __init__(self, device="LFE5U-45F", toolchain="diamond",
sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs):
platform = ulx3s.Platform(device=device, toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
@ -63,10 +63,10 @@ class BaseSoC(SoCSDRAM):
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
sdram_module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
sdram_module.geom_settings,
sdram_module.timing_settings)
# Build --------------------------------------------------------------------------------------------
@ -76,11 +76,18 @@ def main():
help='gateware toolchain to use, diamond (default) or trellis')
parser.add_argument("--device", dest="device", default="LFE5U-45F",
help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F')
parser.add_argument("--sys-clk-freq", default=50e6,
help="system clock frequency (default=50MHz)")
parser.add_argument("--sdram-module", default="MT48LC16M16",
help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(device=args.device, toolchain=args.toolchain, **soc_sdram_argdict(args))
soc = BaseSoC(device=args.device, toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
sdram_module_cls=args.sdram_module,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()