lasmicon: enable refresh at all times

This commit is contained in:
Sebastien Bourdeauducq 2015-09-24 16:01:08 +08:00
parent 9b08b037e4
commit ecdc4101b4
2 changed files with 53 additions and 56 deletions

View File

@ -12,8 +12,7 @@ class LASMIconSettings:
read_time=32, write_time=16, read_time=32, write_time=16,
l2_size=8192, l2_size=8192,
with_bandwidth=False, with_bandwidth=False,
with_memtest=False, with_memtest=False):
with_refresh=True):
self.req_queue_size = req_queue_size self.req_queue_size = req_queue_size
self.read_time = read_time self.read_time = read_time
self.write_time = write_time self.write_time = write_time
@ -23,7 +22,6 @@ class LASMIconSettings:
else: else:
self.with_bandwidth = with_bandwidth self.with_bandwidth = with_bandwidth
self.with_memtest = with_memtest self.with_memtest = with_memtest
self.with_refresh = with_refresh
class LASMIcon(Module): class LASMIcon(Module):
@ -50,7 +48,7 @@ class LASMIcon(Module):
### ###
self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits, self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits,
timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC, enabled=controller_settings.with_refresh) timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i, self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
getattr(self.lasmic, "bank"+str(i))) getattr(self.lasmic, "bank"+str(i)))
for i in range(2**geom_settings.bankbits)] for i in range(2**geom_settings.bankbits)]

View File

@ -6,14 +6,13 @@ from misoc.mem.sdram.core.lasmicon.multiplexer import *
class Refresher(Module): class Refresher(Module):
def __init__(self, a, ba, tRP, tREFI, tRFC, enabled=True): def __init__(self, a, ba, tRP, tREFI, tRFC):
self.req = Signal() self.req = Signal()
self.ack = Signal() # 1st command 1 cycle after assertion of ack self.ack = Signal() # 1st command 1 cycle after assertion of ack
self.cmd = CommandRequest(a, ba) self.cmd = CommandRequest(a, ba)
### ###
if enabled:
# Refresh sequence generator: # Refresh sequence generator:
# PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done # PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
seq_start = Signal() seq_start = Signal()