break down sdram, improve consistency of core names

misoc/cores/lasmicon/test_bankmachine.py

@@ -4,7 +4,7 @@ from migen.sim.generic import run_simulation
 from misoc.mem.sdram.code import lasmibus
 from misoc.mem.sdram.core.lasmicon.bankmachine import *
 
-from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
 
 
 def my_generator():

misoc/cores/lasmicon/test_df.py

@@ -5,7 +5,7 @@ from misoc.mem.sdram.core import lasmibus
 from misoc.mem.sdram.core.lasmicon import *
 from misoc.mem.sdram.frontend import dma_lasmi
 
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 
 
 class TB(Module):

misoc/cores/lasmicon/test_lasmi.py

@@ -4,7 +4,7 @@ from migen.sim.generic import run_simulation
 from misoc.mem.sdram.core import lasmibus
 from misoc.mem.sdram.core.lasmicon import *
 
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 
 
 def my_generator_r(n):

misoc/cores/lasmicon/test_wb.py

@@ -7,7 +7,7 @@ from misoc.mem.sdram.core import lasmibus
 from misoc.mem.sdram.core.lasmicon import *
 from misoc.mem.sdram.frontend import wishbone2lasmi
 
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 
 l2_size = 8192  # in bytes
 

misoc/cores/minicon/__init__.py

@@ -0,0 +1 @@
+from misoc.cores.minicon.core import Minicon, MiniconSettings

misoc/cores/minicon/core.py

@@ -96,7 +96,6 @@ class Minicon(Module):
                                 address_align)
 
         # Manage banks
-        bank_open = Signal()
         bank_idle = Signal()
         bank_hit = Signal()
 

misoc/cores/sdram/__init__.py

@@ -1,11 +0,0 @@
-from collections import namedtuple
-
-PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")
-def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):
-    return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)
-
-GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits")
-def GeomSettings(bankbits, rowbits, colbits):
-    return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits))
-
-TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")

misoc/cores/sdram/core/__init__.py

@@ -1,36 +0,0 @@
-from migen import *
-from migen.genlib.record import *
-from migen.bank.description import *
-
-from misoc.mem.sdram.phy import dfii
-from misoc.mem.sdram.core import minicon, lasmicon
-from misoc.mem.sdram.core import lasmixbar
-
-
-class SDRAMCore(Module, AutoCSR):
-    def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs):
-        # DFI
-        self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
-                phy.settings.dfi_databits, phy.settings.nphases)
-        self.comb += Record.connect(self.dfii.master, phy.dfi)
-
-        # LASMICON
-        if isinstance(controller_settings, lasmicon.LASMIconSettings):
-            self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings,
-                                                                        geom_settings,
-                                                                        timing_settings,
-                                                                        controller_settings,
-                                                                        **kwargs)
-            self.comb += Record.connect(controller.dfi, self.dfii.slave)
-
-            self.submodules.crossbar = lasmixbar.LASMIxbar([controller.lasmic],
-                                                           controller.nrowbits)
-
-        # MINICON
-        elif isinstance(controller_settings, minicon.MiniconSettings):
-            self.submodules.controller = controller = minicon.Minicon(phy.settings,
-                                                                      geom_settings,
-                                                                      timing_settings)
-            self.comb += Record.connect(controller.dfi, self.dfii.slave)
-        else:
-            raise ValueError("Unsupported SDRAM controller type")

misoc/cores/sdram/test/abstract_transactions_lasmi.py

@@ -1,42 +0,0 @@
-from migen import *
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
-
-from misoc.mem.sdram.core import lasmibus
-
-
-def my_generator(n):
-    bank = n % 4
-    for x in range(4):
-        t = TWrite(4*bank+x, 0x1000*bank + 0x100*x)
-        yield t
-        print("{0}: Wrote in {1} cycle(s)".format(n, t.latency))
-
-    for x in range(4):
-        t = TRead(4*bank+x)
-        yield t
-        print("{0}: Read {1:x} in {2} cycle(s)".format(n, t.data, t.latency))
-        assert(t.data == 0x1000*bank + 0x100*x)
-
-
-class MyModel(lasmibus.TargetModel):
-    def read(self, bank, address):
-        r = 0x1000*bank + 0x100*address
-        #print("read from bank {0} address {1} -> {2:x}".format(bank, address, r))
-        return r
-
-    def write(self, bank, address, data, we):
-        print("write to bank {0} address {1:x} data {2:x}".format(bank, address, data))
-        assert(data == 0x1000*bank + 0x100*address)
-
-
-class TB(Module):
-    def __init__(self):
-        self.submodules.controller = lasmibus.Target(MyModel(), aw=4, dw=32, nbanks=4, req_queue_size=4,
-            read_latency=4, write_latency=1)
-        self.submodules.xbar = lasmibus.Crossbar([self.controller.bus], 2)
-        self.initiators = [lasmibus.Initiator(my_generator(n), self.xbar.get_master()) for n in range(4)]
-        self.submodules += self.initiators
-
-if __name__ == "__main__":
-    run_simulation(TB())

misoc/cores/sdram_model.py

@@ -158,7 +158,6 @@ class SDRAMPHYSim(Module):
 
             # bank reads
             reads = Signal(len(phases))
-            read_data = Signal(data_width)
             cases = {}
             for np, phase in enumerate(phases):
                 self.comb += reads[np].eq(phase.read)

misoc/cores/sdram_phy/__init__.py

@@ -0,0 +1,3 @@
+from misoc.cores.sdramphy.gensdrphy import GENSDRPHY
+from misoc.cores.sdramphy.s6ddrphy import S6HalfRateDDRPHY, S6QuarterRateDDRPHY
+from misoc.cores.sdramphy.k7ddrphy import K7DDRPHY

misoc/cores/sdram_settings.py

@@ -1,9 +1,21 @@
-# SDRAM memory modules library
-#
-# This library avoid duplications of memory modules definitions in targets and
-# ease SDRAM usage. (User can only select an already existing module or create
-# one for its board and contribute to this library)
-#
+from math import ceil
+from collections import namedtuple
+
+from migen import *
+from misoc.mem import sdram
+
+
+PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")
+def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):
+    return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)
+
+GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits")
+def GeomSettings(bankbits, rowbits, colbits):
+    return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits))
+
+TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
+
+
 # TODO:
 #   Try to share the maximum information we can between modules:
 #    - ex: MT46V32M16 and MT46H32M16 are almost identical (V=DDR, H=LPDDR)
@@ -14,11 +26,6 @@
 #    - Modules can have different speedgrades, add support for it (and also add
 #      a check to verify clk_freq is in the supported range)
 
-from math import ceil
-
-from migen import *
-from misoc.mem import sdram
-
 
 class SDRAMModule:
     def __init__(self, clk_freq, memtype, geom_settings, timing_settings):

misoc/integration/soc_sdram.py

@@ -2,13 +2,41 @@ from migen import *
 from migen.bus import wishbone
 from migen.genlib.record import *
 
-from misoc.mem.sdram.core import SDRAMCore
 from misoc.mem.sdram.core.lasmicon import LASMIconSettings
 from misoc.mem.sdram.core.minicon import MiniconSettings
 from misoc.mem.sdram.frontend import memtest, wishbone2lasmi
 from misoc.integration.soc_core import SoCCore
 
 
+class SDRAMCore(Module, AutoCSR):
+    def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs):
+        # DFI
+        self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
+                phy.settings.dfi_databits, phy.settings.nphases)
+        self.comb += Record.connect(self.dfii.master, phy.dfi)
+
+        # LASMICON
+        if isinstance(controller_settings, lasmicon.LASMIconSettings):
+            self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings,
+                                                                        geom_settings,
+                                                                        timing_settings,
+                                                                        controller_settings,
+                                                                        **kwargs)
+            self.comb += Record.connect(controller.dfi, self.dfii.slave)
+
+            self.submodules.crossbar = lasmixbar.LASMIxbar([controller.lasmic],
+                                                           controller.nrowbits)
+
+        # MINICON
+        elif isinstance(controller_settings, minicon.MiniconSettings):
+            self.submodules.controller = controller = minicon.Minicon(phy.settings,
+                                                                      geom_settings,
+                                                                      timing_settings)
+            self.comb += Record.connect(controller.dfi, self.dfii.slave)
+        else:
+            raise ValueError("Unsupported SDRAM controller type")
+
+
 class SoCSDRAM(SoCCore):
     csr_map = {
         "sdram":           8,