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Build top module as 'dut' in Verilator and set it as top-level. 

When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.
This commit is contained in:
Sergiusz Bazanski 2018-01-23 01:15:28 +00:00
parent 21bd26dcdd
commit ef6c517dad
2 changed files with 2 additions and 1 deletions
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1
litex/build/sim/core/Makefile
View File

@ -26,6 +26,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
sim: mkdir $(OBJS_SIM) sim: mkdir $(OBJS_SIM)
verilator -Wno-fatal -O3 --cc dut.v --exe \ verilator -Wno-fatal -O3 --cc dut.v --exe \
$(SRCS_SIM_CPP) $(OBJS_SIM) \ $(SRCS_SIM_CPP) $(OBJS_SIM) \
--top-module dut \
-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \ -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
-LDFLAGS "$(LDFLAGS)" \ -LDFLAGS "$(LDFLAGS)" \
-trace $(INC_DIR) -trace $(INC_DIR)

2
litex/build/sim/verilator.py
View File

@ -146,7 +146,7 @@ class SimVerilatorToolchain:
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
platform.finalize(fragment) platform.finalize(fragment)
v_output = platform.get_verilog(fragment) v_output = platform.get_verilog(fragment, name=build_name)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_output.write("dut.v") v_output.write("dut.v")