examples: update & simplify
This commit is contained in:
Florent Kermarrec
parent
b3ae31ee2f
commit
f823d06cf1
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@ -1,15 +1,8 @@
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from migScope import trigger, recorder, migIo
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo
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import spi2Csr
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from spi2Csr.tools.uart2Spi import *
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#==============================================================================
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@ -25,17 +18,17 @@ record_size = 1024
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csr = Uart2Spi(1,115200)
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# Csr Addr
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MIGIO_ADDR = 0x0000
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MIIO_ADDR = 0x0000
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# MigScope Configuration
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# migIo
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr)
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# Miscope Configuration
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# miIo
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miIo0 = miIo.MiIo(MIIO_ADDR, 8, "IO", csr)
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def led_anim0():
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for i in range(10):
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migIo0.write(0xA5)
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miIo0.write(0xA5)
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time.sleep(0.1)
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migIo0.write(0x5A)
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miIo0.write(0x5A)
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time.sleep(0.1)
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def led_anim1():
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@ -43,13 +36,13 @@ def led_anim1():
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for j in range(4):
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ledData = 1
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for i in range(8):
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migIo0.write(ledData)
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miIo0.write(ledData)
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time.sleep(i*i*0.0020)
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ledData = (ledData<<1)
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#Led >>
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ledData = 128
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for i in range(8):
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migIo0.write(ledData)
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miIo0.write(ledData)
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time.sleep(i*i*0.0020)
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ledData = (ledData>>1)
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@ -64,6 +57,6 @@ led_anim1()
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time.sleep(1)
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print("- Read Switch: ",end=' ')
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print(migIo0.read())
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print(miIo0.read())
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@ -1,17 +1,10 @@
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from miscope import trigger, recorder, miIo, miLa
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from miscope.tools.truthtable import *
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from miscope.tools.vcd import *
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo, migLa
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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import spi2Csr
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from spi2Csr.tools.uart2Spi import *
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#==============================================================================
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@ -25,21 +18,21 @@ dat_width = 16
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record_size = 4096
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# Csr Addr
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MIGIO_ADDR = 0x0000
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MIGLA_ADDR = 0x0200
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MIIO_ADDR = 0x0000
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MILA_ADDR = 0x0200
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csr = Uart2Spi(1, 115200, debug=False)
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# MigScope Configuration
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# migIo0
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr)
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# MiScope Configuration
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# miIo0
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miIo0 = miIo.MigIo(MIIO_ADDR, 8, "IO",csr)
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# migIla0
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# miLa0
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(trig_width, [term0])
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recorder0 = recorder.Recorder(dat_width, record_size)
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migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr)
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miLa0 = miLa.MiLa(MILA_ADDR, trigger0, recorder0, csr)
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#==============================================================================
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# T E S T M I G L A
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@ -52,19 +45,19 @@ def capture(size):
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global recorder0
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global dat_vcd
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sum_tt = gen_truth_table("term0")
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migLa0.trig.sum.write(sum_tt)
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migLa0.rec.reset()
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migLa0.rec.offset(0)
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migLa0.rec.arm()
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miLa0.trig.sum.write(sum_tt)
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miLa0.rec.reset()
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miLa0.rec.offset(0)
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miLa0.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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while(not migLa0.rec.is_done()):
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while(not miLa0.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += migLa0.rec.read(size)
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dat_vcd += miLa0.rec.read(size)
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print("[Done]")
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print("Capturing Ramp..")
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@ -87,4 +80,4 @@ capture(1024)
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myvcd = Vcd()
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myvcd.add(Var("wire", 16, "trig_dat", dat_vcd))
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myvcd.write("test_MigLa_0.vcd")
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myvcd.write("test_MiLa_0.vcd")
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@ -1,17 +1,10 @@
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from miscope import trigger, recorder, miIo, miLa
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from miscope.tools.truthtable import *
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from miscope.tools.vcd import *
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo, migLa
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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import spi2Csr
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from spi2Csr.tools.uart2Spi import *
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#==============================================================================
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@ -25,21 +18,21 @@ dat_width = 32
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record_size = 4096
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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MIGLA1_ADDR = 0x0600
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MIIO0_ADDR = 0x0000
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MILA1_ADDR = 0x0600
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csr = Uart2Spi(1, 115200, debug=False)
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# MigScope Configuration
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# migIo0
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr)
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# MiScope Configuration
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# miIo0
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miIo0 = miIo.MigIo(MIIO0_ADDR, 8, "IO",csr)
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# migIla1
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# miLa1
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term1 = trigger.Term(trig_width)
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trigger1 = trigger.Trigger(trig_width, [term1])
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recorder1 = recorder.Recorder(dat_width, record_size)
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migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1, csr)
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miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1, csr)
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#==============================================================================
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# T E S T M I G L A
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@ -49,25 +42,25 @@ recorder1.size(1024)
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term1.write(0x0100005A,0x0100005A)
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sum_tt = gen_truth_table("term1")
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migLa1.trig.sum.write(sum_tt)
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migLa1.rec.reset()
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migLa1.rec.offset(256)
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migLa1.rec.arm()
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miLa1.trig.sum.write(sum_tt)
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miLa1.rec.reset()
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miLa1.rec.offset(256)
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miLa1.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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csr.write(0x0000,0x5A)
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while(not migLa1.rec.is_done()):
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while(not miLa1.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += migLa1.rec.read(1024)
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dat_vcd += miLa1.rec.read(1024)
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print("[Done]")
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myvcd = Vcd()
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myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8)))
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myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24)))
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myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24)))
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myvcd.write("test_MigLa_1.vcd")
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myvcd.write("test_MiLa_1.vcd")
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@ -1,15 +1,8 @@
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from migScope import trigger, recorder, migIo
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo
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import spi2Csr
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from spi2Csr.tools.uart2Spi import *
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#==============================================================================
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@ -25,17 +18,17 @@ record_size = 1024
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csr = Uart2Spi(1,115200)
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# Csr Addr
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MIGIO_ADDR = 0x0000
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MIIO_ADDR = 0x0000
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# MigScope Configuration
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# migIo
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr)
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# Miscope Configuration
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# miIo
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miIo0 = miIo.MiIo(MIIO_ADDR, 8, "IO", csr)
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def led_anim0():
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for i in range(10):
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migIo0.write(0xA5)
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miIo0.write(0xA5)
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time.sleep(0.1)
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migIo0.write(0x5A)
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miIo0.write(0x5A)
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time.sleep(0.1)
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def led_anim1():
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@ -43,13 +36,13 @@ def led_anim1():
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for j in range(4):
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ledData = 1
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for i in range(8):
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migIo0.write(ledData)
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miIo0.write(ledData)
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time.sleep(i*i*0.0020)
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ledData = (ledData<<1)
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#Led >>
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ledData = 128
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for i in range(8):
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migIo0.write(ledData)
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miIo0.write(ledData)
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time.sleep(i*i*0.0020)
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ledData = (ledData>>1)
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@ -64,6 +57,6 @@ led_anim1()
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time.sleep(1)
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print("- Read Switch: ",end=' ')
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print(migIo0.read())
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print(miIo0.read())
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@ -1,17 +1,10 @@
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from miscope import trigger, recorder, miIo, miLa
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from miscope.tools.truthtable import *
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from miscope.tools.vcd import *
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo, migLa
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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import spi2Csr
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from spi2Csr.tools.uart2Spi import *
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#==============================================================================
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@ -25,21 +18,21 @@ dat_width = 16
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record_size = 4096
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# Csr Addr
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MIGIO_ADDR = 0x0000
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MIGLA_ADDR = 0x0200
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MIIO_ADDR = 0x0000
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MILA_ADDR = 0x0200
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csr = Uart2Spi(1, 115200, debug=False)
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# MigScope Configuration
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# migIo0
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr)
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# MiScope Configuration
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# miIo0
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miIo0 = miIo.MigIo(MIIO_ADDR, 8, "IO",csr)
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# migIla0
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# miLa0
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(trig_width, [term0])
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recorder0 = recorder.Recorder(dat_width, record_size)
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migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr)
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miLa0 = miLa.MiLa(MILA_ADDR, trigger0, recorder0, csr)
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#==============================================================================
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# T E S T M I G L A
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@ -52,19 +45,19 @@ def capture(size):
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global recorder0
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global dat_vcd
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sum_tt = gen_truth_table("term0")
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migLa0.trig.sum.write(sum_tt)
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migLa0.rec.reset()
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migLa0.rec.offset(0)
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migLa0.rec.arm()
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miLa0.trig.sum.write(sum_tt)
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miLa0.rec.reset()
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miLa0.rec.offset(0)
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miLa0.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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while(not migLa0.rec.is_done()):
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while(not miLa0.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += migLa0.rec.read(size)
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dat_vcd += miLa0.rec.read(size)
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print("[Done]")
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print("Capturing Ramp..")
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@ -87,4 +80,4 @@ capture(1024)
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myvcd = Vcd()
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myvcd.add(Var("wire", 16, "trig_dat", dat_vcd))
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myvcd.write("test_MigLa_0.vcd")
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myvcd.write("test_MiLa_0.vcd")
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@ -1,17 +1,10 @@
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from miscope import trigger, recorder, miIo, miLa
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from miscope.tools.truthtable import *
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from miscope.tools.vcd import *
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo, migLa
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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import spi2Csr
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from spi2Csr.tools.uart2Spi import *
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#==============================================================================
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@ -25,21 +18,21 @@ dat_width = 32
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record_size = 4096
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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MIGLA1_ADDR = 0x0600
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MIIO0_ADDR = 0x0000
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MILA1_ADDR = 0x0600
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csr = Uart2Spi(1, 115200, debug=False)
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# MigScope Configuration
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# migIo0
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr)
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# MiScope Configuration
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# miIo0
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miIo0 = miIo.MigIo(MIIO0_ADDR, 8, "IO",csr)
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# migIla1
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# miLa1
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term1 = trigger.Term(trig_width)
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trigger1 = trigger.Trigger(trig_width, [term1])
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recorder1 = recorder.Recorder(dat_width, record_size)
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migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1, csr)
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miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1, csr)
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#==============================================================================
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# T E S T M I G L A
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@ -49,25 +42,25 @@ recorder1.size(1024)
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term1.write(0x0100005A,0x0100005A)
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sum_tt = gen_truth_table("term1")
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migLa1.trig.sum.write(sum_tt)
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migLa1.rec.reset()
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migLa1.rec.offset(256)
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migLa1.rec.arm()
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miLa1.trig.sum.write(sum_tt)
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miLa1.rec.reset()
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miLa1.rec.offset(256)
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miLa1.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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csr.write(0x0000,0x5A)
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while(not migLa1.rec.is_done()):
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while(not miLa1.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += migLa1.rec.read(1024)
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dat_vcd += miLa1.rec.read(1024)
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||||
print("[Done]")
|
||||
|
||||
myvcd = Vcd()
|
||||
myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8)))
|
||||
myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24)))
|
||||
myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24)))
|
||||
myvcd.write("test_MigLa_1.vcd")
|
||||
myvcd.write("test_MiLa_1.vcd")
|
||||
Loading…
Reference in New Issue