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wishbone/Cache: avoid REFILL_WRTAG state to improve speed.

This commit is contained in:
Florent Kermarrec 2020-01-10 12:52:14 +01:00
parent f408527dd4
commit fa22d6aa82
1 changed files with 8 additions and 8 deletions
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16
litex/soc/interconnect/wishbone.py
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@ -606,7 +606,10 @@ class Cache(Module):
If(tag_do.dirty,
NextState("EVICT")
).Else(
NextState("REFILL_WRTAG")
# Write the tag first to set the slave address
tag_port.we.eq(1),
word_clr.eq(1),
NextState("REFILL")
)
)
)
@ -618,16 +621,13 @@ class Cache(Module):
If(slave.ack,
word_inc.eq(1),
If(word_is_last(word),
NextState("REFILL_WRTAG")
# Write the tag first to set the slave address
tag_port.we.eq(1),
word_clr.eq(1),
NextState("REFILL")
)
)
)
fsm.act("REFILL_WRTAG",
# Write the tag first to set the slave address
tag_port.we.eq(1),
word_clr.eq(1),
NextState("REFILL")
)
fsm.act("REFILL",
slave.stb.eq(1),
slave.cyc.eq(1),