Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

CHANGES: Update.

This commit is contained in:
Florent Kermarrec 2023-10-27 11:40:31 +02:00
parent e55cf0f6d9
commit fa629b782f
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
CHANGES.md
View File

@ -4,6 +4,7 @@
--------
- liteeth/arp : Fixed response on table update.
- litesata/us(p)sataphy : Fixed data_width=32 case.
- clock/lattice_ecp5 : Fixed phase calculation.
[> Added
--------
@ -18,6 +19,7 @@
- soc/cores : Added Ti60F100 HyperRAM support.
- build/xilinx : Added initial OpenXC7 support (and improved Yosys-NextPnr).
- build/efinix : Added JTAG-UART/JTAGBone support.
- interconnect/wishbone : Added byte/word addressing support.
[> Changed
----------