Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/cores/clock: remove return on S7PLL.create_clkout

This commit is contained in:
Florent Kermarrec 2018-12-19 09:14:26 +01:00
parent eda1a83ea9
commit fe5cef4294
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/cores/clock.py
View File

@ -60,8 +60,6 @@ class S7Clocking(Module, AutoCSR):
else: else:
raise ValueError raise ValueError
return clkout_buf
def compute_config(self): def compute_config(self):
config = {} config = {}
config["divclk_divide"] = 1 config["divclk_divide"] = 1