soc/cores/clock: remove return on S7PLL.create_clkout

2018-12-19 09:14:26 +01:00 · 2018-12-19 09:14:26 +01:00 · fe5cef4294
parent eda1a83ea9
commit fe5cef4294
1 changed files with 0 additions and 2 deletions
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@ -60,8 +60,6 @@ class S7Clocking(Module, AutoCSR):
            else:
                raise ValueError

-        return clkout_buf
-
    def compute_config(self):
        config = {}
        config["divclk_divide"] = 1