5 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	d280723618	examples/fir: print Verilog source	2012-06-08 14:00:49 +02:00
Sebastien Bourdeauducq	b00e8fa826	examples/fir: plot input and output signals	2012-06-07 23:20:59 +02:00
Sebastien Bourdeauducq	081b658e2d	Update copyright notices	2012-03-23 16:41:30 +01:00
Sebastien Bourdeauducq	f6e76ae198	doc: more examples and comments	2012-03-10 19:38:39 +01:00
Sebastien Bourdeauducq	57a87b3316	examples: FIR filter simulation	2012-03-08 20:49:36 +01:00