Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
990 Commits 40 Branches 14 Tags 51 MiB
Commit Graph

21 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 264bc61e04 genlib/fifo: add replace command to sync FIFO 2014-09-10 21:19:15 +08:00
Sebastien Bourdeauducq 8baa957539 genlib/fifo: use synchronous memory read instead of additional register 
The latter causes problems with InsertReset
 2014-08-02 08:52:49 +08:00
Sebastien Bourdeauducq ff1d105c7e genlib/SyncFIFO: remove flush signal (use InsertReset instead) 2014-07-17 19:15:45 -06:00
Florent Kermarrec 4c426b36f3 fifo: add support for depth=2 2014-06-15 23:58:46 +02:00
Robert Jordens ac1363565d genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered 2014-04-05 12:15:14 +02:00
Robert Jordens b03d9f4c14 genlib/fifo: add flush, expose level in SyncFIFO 
AsyncFIFO would need versions of flush and level in each clock domain
plus some handshaking on double flush.

Signed-off-by: Robert Jordens <jordens@gmail.com>
 2014-03-15 23:10:46 -07:00
Robert Jördens 502a2871bc test/test_fifo, genlib/fifo: move test to unittest 2013-11-29 23:11:53 +01:00
Robert Jördens e469e5e539 genlib.fifo: fix docstring section syntax 2013-11-29 22:31:51 +01:00
Sebastien Bourdeauducq e1b31ec455 genlib/fifo: clarify we behaviour when writable=0 2013-11-28 22:31:10 +01:00
Robert Jordens 6e9e0a60eb setup API documentation, start by documenting fifos 2013-11-28 22:14:20 +01:00
Sebastien Bourdeauducq b782db14fc Revert "genlib/fifo: support RecordP" 
This reverts commit c0d2b5a789.
 2013-10-22 15:22:40 +02:00
Sebastien Bourdeauducq c0d2b5a789 genlib/fifo: support RecordP 2013-10-21 22:30:06 +02:00
Sebastien Bourdeauducq 9c7ad6b05b fhdl: RenameClockDomains decorator 2013-07-26 15:42:14 +02:00
David Carne 9190568685 genlib/fifo/AsyncFIFO: fix data corruption bug 2013-07-17 12:10:39 +02:00
Sebastien Bourdeauducq 7083764b53 genlib/fifo: add test bench 2013-07-15 21:36:39 +02:00
Sebastien Bourdeauducq 5cd0019231 genlib/fifo: support records 2013-06-17 23:35:10 +02:00
Sebastien Bourdeauducq bac62a32a9 Make memory ports part of specials 
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
 2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq 70ffe86356 New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq e97edd7253 genlib/fifo: disable retiming on Gray counter outputs 2013-04-25 14:57:07 +02:00
Sebastien Bourdeauducq 67c3119249 genlib/fifo: add asynchronous FIFO 2013-04-25 13:30:37 +02:00
Sebastien Bourdeauducq 9d7c679b8c genlib/fifo: simple synchronous FIFO 2013-03-22 18:18:38 +01:00