6 commits

Author	SHA1	Message	Date
Werner Almesberger	7a6e56492c	edid.py: sample SCL only every 64 clock cycles, to avoid bouncing ... Possibly due to SCL rising fairly slowly (in the 0.5-1 us range), bouncing has been observed while crossing the "forbidden" region between Vil(max) and Vih(min). By lowering the sample rate from once per system clock to once every 64 clock cycles, we make sure we sample at most once during the bounce interval and thus never see a false edge. (Although we may see a rising edge one sample time late, which is perfectly harmless.)	2013-04-12 22:48:46 +02:00
Sebastien Bourdeauducq	4f4f260e76	Convert to new CSR API	2013-03-30 17:28:15 +01:00
Sebastien Bourdeauducq	1e860c7472	Use new Mibuild generic_platform API	2013-03-26 17:57:17 +01:00
Sebastien Bourdeauducq	e06585d9fe	dvisampler: clean up EDID data	2013-03-23 13:48:40 +01:00
Sebastien Bourdeauducq	0168f83523	MultiReg: remove idomain	2013-03-15 19:51:29 +01:00
Sebastien Bourdeauducq	e99bafe52b	dvisampler: add core, EDID support	2013-03-13 19:56:26 +01:00