Sebastien Bourdeauducq
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17b2588321
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ddrphy: reads OK, write data coming out 1/2 cycle too late
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2012-02-24 15:05:52 +01:00 |
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Sebastien Bourdeauducq
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a363eb4a36
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ddrphy: partly working
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2012-02-24 13:54:10 +01:00 |
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Sebastien Bourdeauducq
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b3ca952a39
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s6ddrphy: read path OK in simulation
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2012-02-21 17:38:40 +01:00 |
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Sebastien Bourdeauducq
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b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
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ce51653381
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s6ddrphy: generate DQ/DQS/DM OE
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2012-02-20 16:13:56 +01:00 |
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Sebastien Bourdeauducq
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cbc3b7fa83
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s6ddrphy: DQ/DQS/DM SERDES
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2012-02-20 13:45:57 +01:00 |
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Sebastien Bourdeauducq
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4c1e18a9b5
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s6ddrphy: clock, address and command
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2012-02-19 20:49:56 +01:00 |
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Sebastien Bourdeauducq
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f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |