10 commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	28f00c3a9a	Add on-chip SRAM	2012-01-27 22:09:03 +01:00
Sebastien Bourdeauducq	6fde54c5aa	Use meaningful class names	2012-01-21 12:25:22 +01:00
Sebastien Bourdeauducq	f6aa95a4d0	Use new verilog.convert API	2012-01-20 23:00:11 +01:00
Sebastien Bourdeauducq	570ea8ccf8	convtools -> tools	2012-01-13 17:07:46 +01:00
Sebastien Bourdeauducq	b60abfaa4a	Convert -> convert	2012-01-05 19:27:45 +01:00
Sebastien Bourdeauducq	6664af73d1	uart: new design using FHDL and bank (TX only, incomplete)	2011-12-18 00:29:37 +01:00
Sebastien Bourdeauducq	0e30d67fa3	Multiply system clock	2011-12-17 15:00:18 +01:00
Sebastien Bourdeauducq	411e1af980	Proper reset generation	2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq	ca68097ef6	Pay a bit more attention to PEP8	2011-12-16 16:02:49 +01:00
Sebastien Bourdeauducq	b487e99bcf	Initial import	2011-12-13 17:33:12 +01:00