Sebastien Bourdeauducq
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19abe2b888
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k7ddrphy: do not register T at SERDES (fixes timing problem)
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2014-08-31 21:53:35 +08:00 |
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Sebastien Bourdeauducq
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541e5abbc7
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k7ddrphy: update comment
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2014-08-22 19:02:57 +08:00 |
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Sebastien Bourdeauducq
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66fe45ba96
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k7ddrphy: decrease CAS latency to account for cmd/data flight time
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2014-08-22 18:46:01 +08:00 |
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Sebastien Bourdeauducq
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b94647ab16
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k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter
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2014-08-22 18:45:25 +08:00 |
Florent Kermarrec
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1c381acc6f
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k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)
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2014-08-14 22:46:06 +08:00 |
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Florent Kermarrec
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acbba37f5f
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k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim)
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2014-08-14 22:46:06 +08:00 |
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Florent Kermarrec
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2e4bfe154f
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k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay)
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2014-08-14 22:46:06 +08:00 |
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Florent Kermarrec
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bb85f29f91
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k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe
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2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
9844c25df9
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k7ddrphy: add SERDES reset
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2014-08-14 14:16:41 +08:00 |
|
Sebastien Bourdeauducq
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c8dd4d2b40
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k7ddrphy: send rddata_valid on all phases
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2014-08-09 11:00:13 +08:00 |
|
Sebastien Bourdeauducq
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a2c7ff4c0c
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sdramphy: initial K7 DDR3 support
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2014-08-08 21:28:26 +08:00 |