litex

Commit Graph

Author	SHA1	Message	Date
Jiaxun Yang	c52a2ca5df	soc/integration/soc: Fix CSRBridge Bus Width conversion Wishbone2CSR and AXILite2CSR bridges are incapable for performing bus width conversion, which means it's Bus slave port must have same width as CSRs. Use CSR width to create slave bus to allow width adaptar to be inserted by add_slave. Also add relevant assertion. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>	2024-12-18 10:29:33 +00:00
Florent Kermarrec	002aad7a43	soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.	2023-10-27 10:55:13 +02:00
Ilia Sergachev	65d5161408	test/axi_lite: parametrize address and data width in another test; add another test call with 64b data width	2022-07-20 02:44:57 +02:00
Ilia Sergachev	bffd59726c	test/axi_lite: rename a test for clarity; parametrize address and data width; add another test call with 64b data width	2022-07-20 02:43:43 +02:00
Florent Kermarrec	77ae243310	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
Florent Kermarrec	a5d0a340c3	test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.	2020-08-04 09:39:23 +02:00
Jędrzej Boczar	e78d950a31	soc/interconnect/axi: add AXILite -> AXI converter	2020-07-30 13:50:34 +02:00
Jędrzej Boczar	879e6ffe73	soc/interconnect/axi: add basic AXI Lite up-converter	2020-07-24 13:47:18 +02:00
Jędrzej Boczar	32160e615f	soc/interconnect/axi: separate AXI Lite converter channels	2020-07-24 09:25:57 +02:00
Jędrzej Boczar	a9d8b81385	test/axi: move all AXI Lite tests to separate file	2020-07-22 17:16:33 +02:00
Florent Kermarrec	67159349d6	soc/interconnect: remove axi_lite axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI support and it also cover what axi_lite was doing: To create a AXILite to CSR bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus directly to the wishbone bus as done in the others non-AXI SoC.	2019-05-11 09:12:20 +02:00
Florent Kermarrec	b7f53fb93c	test: remove waveforms generation	2019-04-22 08:41:28 +02:00
Florent Kermarrec	ed2578799b	test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)	2019-02-27 22:24:56 +01:00

13 Commits