Sebastien Bourdeauducq
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f6aa95a4d0
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Use new verilog.convert API
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2012-01-20 23:00:11 +01:00 |
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Sebastien Bourdeauducq
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570ea8ccf8
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convtools -> tools
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2012-01-13 17:07:46 +01:00 |
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Sebastien Bourdeauducq
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b60abfaa4a
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Convert -> convert
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2012-01-05 19:27:45 +01:00 |
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Sebastien Bourdeauducq
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6664af73d1
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uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
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0e30d67fa3
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Multiply system clock
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2011-12-17 15:00:18 +01:00 |
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Sebastien Bourdeauducq
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411e1af980
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Proper reset generation
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2011-12-16 22:25:26 +01:00 |
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Sebastien Bourdeauducq
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ca68097ef6
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Pay a bit more attention to PEP8
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2011-12-16 16:02:49 +01:00 |
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Sebastien Bourdeauducq
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b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |