Florent Kermarrec
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79dbb6da4b
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replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows)
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2015-01-19 09:45:34 +01:00 |
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Florent Kermarrec
|
6de7e15a0c
|
refactor code
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2015-01-17 13:22:52 +01:00 |
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Florent Kermarrec
|
6f2c7a236c
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add support of identify device command
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2015-01-17 02:35:25 +01:00 |
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Florent Kermarrec
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c227576f3d
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add test_link.py (replace test_bist_mila)
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2015-01-16 21:16:05 +01:00 |
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Florent Kermarrec
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083bd54121
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global clean up
- remove initial sims
- remove SATAPHYDeviceCtrl
- rename to LiteSATA
- rename test to bist
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2015-01-16 20:26:15 +01:00 |
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Florent Kermarrec
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7e31ef2152
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init with repo with simple TestDesign
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2014-09-22 13:36:43 +02:00 |