Florent Kermarrec
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4e3190120e
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fix build with upstream Migen/MiSoC
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2015-01-22 21:23:14 +01:00 |
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Florent Kermarrec
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b299116ace
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replace SATAX with sata_genx
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2015-01-22 17:15:12 +01:00 |
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Florent Kermarrec
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3346bf8b2b
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frontend: simplify
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2015-01-22 10:45:11 +01:00 |
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Florent Kermarrec
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2bb9c6b649
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add verilog backend to use the core with a "standard" flow
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2015-01-19 20:38:48 +01:00 |
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Florent Kermarrec
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d84ae7c80c
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clean up
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2015-01-19 18:13:43 +01:00 |
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Florent Kermarrec
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79dbb6da4b
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replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows)
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2015-01-19 09:45:34 +01:00 |