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1350 commits 42 branches 14 tags 31 MiB
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4 commits

Author SHA1 Message Date
Sebastien Bourdeauducq
8534562185 sim: fix slice assign 2015-09-22 20:33:44 +08:00
Sebastien Bourdeauducq
2c1553fea2 sim: insert resets, support ClockSignal and ResetSignal 2015-09-21 22:13:36 +08:00
Sebastien Bourdeauducq
99af825a5a sim: drive clock signals 2015-09-21 21:53:41 +08:00
Sebastien Bourdeauducq
a67b4baa0c sim: VCD output support 2015-09-21 21:20:31 +08:00
Renamed from migen/sim.py (Browse further)