Florent Kermarrec
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9960ca010a
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test on hardware and clean up/fix
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2015-01-23 13:27:40 +01:00 |
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Florent Kermarrec
|
b299116ace
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replace SATAX with sata_genx
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2015-01-22 17:15:12 +01:00 |
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Florent Kermarrec
|
8d16a166c4
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change submodules/specials/clock_domains syntax
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2015-01-22 16:04:53 +01:00 |
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Florent Kermarrec
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3346bf8b2b
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frontend: simplify
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2015-01-22 10:45:11 +01:00 |
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Florent Kermarrec
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91bb531641
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bist: add loops parameter for more precision in speed computation
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2015-01-22 01:33:02 +01:00 |
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Florent Kermarrec
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c9761be54f
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command: remove success/failed redundancy (keep failed)
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2015-01-22 00:23:11 +01:00 |
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Florent Kermarrec
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ff0c8e3d22
|
add PacketBuffer, simplify architecture and reduce ressource usage
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2015-01-22 00:13:19 +01:00 |
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Florent Kermarrec
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ebf1faed5b
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transport: simplify tx and reduce ressource usage
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2015-01-21 19:11:54 +01:00 |
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Florent Kermarrec
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1b20831541
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transport: simplify and reduce ressource usage
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2015-01-21 18:55:42 +01:00 |
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Florent Kermarrec
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fccf2c9430
|
common: clean up
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2015-01-21 12:01:28 +01:00 |
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Florent Kermarrec
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f0f6183c9a
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link/crc: use OrderedDict to generate the same code on each iteration
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2015-01-21 11:48:06 +01:00 |
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Florent Kermarrec
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5825ec8f47
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command: merge 2 states on tx
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2015-01-21 10:52:56 +01:00 |
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Florent Kermarrec
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578903bc11
|
manage reg_d2h errors
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2015-01-20 19:28:56 +01:00 |
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Florent Kermarrec
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2bb9c6b649
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add verilog backend to use the core with a "standard" flow
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2015-01-19 20:38:48 +01:00 |
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Florent Kermarrec
|
d84ae7c80c
|
clean up
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2015-01-19 18:13:43 +01:00 |
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Florent Kermarrec
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6de7e15a0c
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refactor code
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2015-01-17 13:22:52 +01:00 |