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4336 Commits

Author SHA1 Message Date
Sean Cross e2cf45b8a9 cpu: vexriscv: allow cpu_reset_address to be overridden 
Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal.  That way the reset address can be modified after
synthesis, in dual-core or debug situations.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-19 13:04:57 +08:00
Florent Kermarrec a92e90b215 soc/interconnect: add avalon with converters to/from native streams 2019-04-18 18:42:29 +02:00
enjoy-digital d860eeea4f
Merge pull request #162 from antmicro/full-conf-vexriscv 
Add full and full_debug CPU variant of VexRiscv
 2019-04-17 19:01:55 +02:00
enjoy-digital ce81a39ce9
Merge pull request #163 from gsomlo/gls-verilated-cmdargs 
build/sim/core: Initialize Verilator commandArgs
 2019-04-17 18:59:28 +02:00
Gabriel L. Somlo e1683078ec build/sim/core: Initialize Verilator commandArgs 
Required when DUT is using plusargs. Prevents Verilator simulation
from crashing with "Verilog called $test$plusargs or $value$plusargs
without testbench C first calling Verilated::commandArgs(argc,argv)".
 2019-04-17 10:39:35 -04:00
Joanna Brozek 40de01bcb0 vexriscv: Add full and full_debug CPU variant 2019-04-17 09:09:35 +02:00
Florent Kermarrec 017147c623 build/altera: switch to sdc constraints, add add_false_path_constraints method 2019-04-16 16:57:23 +02:00
Florent Kermarrec 1275e2f150 build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints 
MultiReg/AsyncResetSynchronizer are not necessarily present in all design, set
quiet property to avoid generating false warnings.
 2019-04-15 16:48:47 +02:00
Florent Kermarrec c252972bef soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale 2019-04-15 11:36:42 +02:00
Florent Kermarrec f986974d60 soc/cores/clock: improve presentation 2019-04-15 10:57:00 +02:00
Florent Kermarrec 538ca59ab6 build/xilinx/vivado: round period constraints to lowest picosecond 
Vivado will do the opposite if we don't do it, with this change we ensure the applied period constraints will always be >= to the requested constraint.
 2019-04-15 10:51:17 +02:00
enjoy-digital 66a74b1579
Merge pull request #161 from enjoy-digital/litex_server_arguments 
litex_server: refactor parameters and to allow setting bind address
 2019-04-15 08:24:28 +02:00
Florent Kermarrec a2bc4bb777 litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination 2019-04-15 08:23:27 +02:00
Florent Kermarrec be99083e2b litex_server: add message and exit when mandarory arguments are missing. 2019-04-14 14:00:35 +02:00
Florent Kermarrec db11aec961 litex_server: allow setting bind port, remove auto-incrementing on bind_port 2019-04-14 12:48:49 +02:00
Florent Kermarrec 76bc57851b litex_server: refactor parameters and to allow setting bind address 
In some cases, it can be useful to bind to "0.0.0.0" instead of "localhost".
While adding bind address support, parameters passing has also been refactored
to ease adding parameters in the future.
 2019-04-14 09:00:08 +02:00
Florent Kermarrec 13a76ec7fb software/libnet/microudp: simplify txbuffer managment 2019-04-12 18:47:31 +02:00
Florent Kermarrec 3441eb05cb software/libnet/microudp: cleanup eth_init 2019-04-12 17:15:09 +02:00
Florent Kermarrec 92a79c6dc1 software/libnet/microudp: simplify rxbuffer managment 2019-04-12 17:14:07 +02:00
Florent Kermarrec fdeff7f64f software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE 2019-04-12 17:09:50 +02:00
Florent Kermarrec 1569e2e0cf software/libnet: remove use of ethmac_mem.h 2019-04-12 17:08:29 +02:00
Florent Kermarrec c7ac96761c bios/sdram: add __attribute__((unused)) on cdelay 2019-04-11 22:26:58 +02:00
Florent Kermarrec 7e53bff39d litex_setup: add litesata 2019-04-10 18:04:48 +02:00
Florent Kermarrec 792245f196 boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter) 2019-04-10 16:36:49 +02:00
Florent Kermarrec f8dcdb70d2 software/libnet: add #ifdef on eth_init 2019-04-10 16:16:47 +02:00
enjoy-digital e475cfbb7d
Merge pull request #158 from vbuitvydas/altera-contrib 
Changes for litepcie support for Altera Cyclone V
 2019-04-08 14:32:44 +02:00
vytautasb 04939990ac litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name 2019-04-08 14:07:10 +03:00
vytautasb 8558065fca litex/build/altera/common: added reset synchronizer 2019-04-08 14:06:24 +03:00
Florent Kermarrec 866fa34493 integration/soc_zynq: fix missing SoCCore.do_finalize 
Signed-off-by: Florent Kermarrec <florent@enjoy-digital.fr>
 2019-04-01 14:44:37 +02:00
Florent Kermarrec 794c3c5860 integration/soc_zynq: add add_hp0 method 2019-04-01 11:10:35 +02:00
Florent Kermarrec 38d404c3cb integration/soc_zynq: use add methods to add optional peripherals 2019-04-01 10:50:04 +02:00
Florent Kermarrec 7375856bec integration/soc_zynq: connect axi signals that were missing 2019-04-01 10:31:33 +02:00
Florent Kermarrec b15fd9d834 interconnect/axi: add missing axi signals 2019-04-01 10:23:25 +02:00
enjoy-digital f95748d167
Merge pull request #157 from CBJamo/master 
Add ifdef check for MAIN_RAM_SIZE
 2019-03-31 18:46:07 +02:00
Caleb Jamison 1f0b3f8124 Add ifdef check for MAIN_RAM_SIZE 2019-03-31 10:33:39 -05:00
Florent Kermarrec f452d3e96f README: bump copyright year 2019-03-30 12:27:06 +01:00
Florent Kermarrec dd214d2d21 bios/main: align SoC info, show CPU speed on CPU line, show L2 2019-03-30 11:49:39 +01:00
Florent Kermarrec 6599f7bb50 bios/main: move sdrinit 2019-03-30 10:56:17 +01:00
Florent Kermarrec b92b89ab92 bios/main: print boot sequence only if sdr_ok 2019-03-30 10:19:00 +01:00
Florent Kermarrec f4369c8fb2 bios/main: remove csr functions (not used and only supported by lm32), improve help presentation 2019-03-29 19:40:24 +01:00
Florent Kermarrec 66dffb7071 software/bios: improve readibility, add soc informations 2019-03-29 00:51:16 +01:00
enjoy-digital e8559990b6
Merge pull request #156 from gsomlo/gls-axi-width 
soc/interconnect/axi: address length cleanup
 2019-03-28 18:27:36 +01:00
Gabriel L. Somlo 449632e430 soc/interconnect/axi: data/address length cleanup 
Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
 2019-03-27 16:52:52 -04:00
Florent Kermarrec 552b0243b3 soc/interconnect/axi: remove dead code (thanks gsomlo) 2019-03-27 21:15:14 +01:00
enjoy-digital b682dacdd7
Merge pull request #154 from daveshah1/yosys_xilinx_edif 
build/xilinx: Update Yosys write_edif parameters
 2019-03-22 17:43:40 +01:00
David Shah 57e1ccd5f8 build/xilinx: Update Yosys write_edif parameters 2019-03-22 16:06:52 +00:00
Florent Kermarrec fd7ed6c1ec utils/litex_sim: fix main_ram_size 2019-03-16 21:25:02 +01:00
Florent Kermarrec 3f386dad7d soc_core/get_mem_data: add json support 
example of json file:
{
    "vmlinux.bin":    "0x00000000",
    "vmlinux.dtb":    "0x01000000",
    "initramdisk.gz": "0x01002000"
}
 2019-03-16 21:23:36 +01:00
Florent Kermarrec 7bc13ba841 build/microsemi/libero_soc: add linux build script support 2019-03-16 09:33:16 +01:00
Florent Kermarrec 7b88980d06 vexriscv: allow user to use an external variant 2019-03-15 18:16:25 +01:00