0b3c4b50fa
soc/cores/spi: add optional aligned mode.
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In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
41fe7cae0b
core/spi: add minimal SPISlave
2019-08-29 09:46:20 +02:00
ea619e3afe
cores/spi: rename add_control paramter to add_csr
2019-07-20 12:56:37 +02:00
769d15d433
cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test
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Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).
2019-07-13 12:55:19 +02:00
6b82f23ce1
cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency.
2019-07-05 15:50:58 +02:00
Florent Kermarrec