litex

Author	SHA1	Message	Date
Sebastien Bourdeauducq	bac62a32a9	Make memory ports part of specials This is needed to handle cases where a single memory has ports in two different modules, and one of these modules is subject to clock domain remapping. The clock domain of the port in that module only must be remapped.	2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq	70ffe86356	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq	e97edd7253	genlib/fifo: disable retiming on Gray counter outputs	2013-04-25 14:57:07 +02:00
Sebastien Bourdeauducq	67c3119249	genlib/fifo: add asynchronous FIFO	2013-04-25 13:30:37 +02:00
Sebastien Bourdeauducq	9d7c679b8c	genlib/fifo: simple synchronous FIFO	2013-03-22 18:18:38 +01:00