8 Commits

Author	SHA1	Message	Date
Florent Kermarrec	a5d0a340c3	test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.	2020-08-04 09:39:23 +02:00
Jędrzej Boczar	e78d950a31	soc/interconnect/axi: add AXILite -> AXI converter	2020-07-30 13:50:34 +02:00
Jędrzej Boczar	879e6ffe73	soc/interconnect/axi: add basic AXI Lite up-converter	2020-07-24 13:47:18 +02:00
Jędrzej Boczar	32160e615f	soc/interconnect/axi: separate AXI Lite converter channels	2020-07-24 09:25:57 +02:00
Jędrzej Boczar	a9d8b81385	test/axi: move all AXI Lite tests to separate file	2020-07-22 17:16:33 +02:00
Florent Kermarrec	67159349d6	soc/interconnect: remove axi_lite ... axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI support and it also cover what axi_lite was doing: To create a AXILite to CSR bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus directly to the wishbone bus as done in the others non-AXI SoC.	2019-05-11 09:12:20 +02:00
Florent Kermarrec	b7f53fb93c	test: remove waveforms generation	2019-04-22 08:41:28 +02:00
Florent Kermarrec	ed2578799b	test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)	2019-02-27 22:24:56 +01:00