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4 commits

Author SHA1 Message Date
Sebastien Bourdeauducq
70ffe86356 New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq
92b67df41c sim: default runner to Icarus Verilog 2013-02-09 17:04:53 +01:00
Sebastien Bourdeauducq
86090e1cbd bus/asmibus: swap port position to be consistent with wishbone API 2012-11-17 19:42:39 +01:00
Sebastien Bourdeauducq
973c00938d Reorganize examples folder 2012-06-12 17:49:50 +02:00
Renamed from examples/abstract_transactions.py (Browse further)