Sebastien Bourdeauducq
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e1702c422c
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introduce conversion output object (prevents file IO in FHDL backends)
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2015-04-08 20:28:23 +08:00 |
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Sebastien Bourdeauducq
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c169f0b189
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Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
This reverts commit f03aa76292.
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2015-03-30 19:41:16 +08:00 |
Florent Kermarrec
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f03aa76292
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migen: create VerilogConvert and EDIFConvert classes and return it with convert functions
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2015-03-30 11:37:55 +02:00 |
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Florent Kermarrec
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dbaeaf7833
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remove trailing whitespaces
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2014-10-17 17:08:46 +08:00 |
Nina Engelhardt
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efa7dc9cf4
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fhdl/edif: adjust for use with mibuild
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2013-08-03 10:54:06 +02:00 |
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Nina Engelhardt
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7372c7a97c
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fhdl/edif: add support for inout signals
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2013-08-03 10:51:24 +02:00 |
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Nina Engelhardt
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17002fb05e
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fhdl: add EDIF back-end
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2013-07-31 22:47:43 +02:00 |