3 Commits

Author	SHA1	Message	Date
Florent Kermarrec	2bb9c6b649	add verilog backend to use the core with a "standard" flow	2015-01-19 20:38:48 +01:00
Florent Kermarrec	d84ae7c80c	clean up	2015-01-19 18:13:43 +01:00
Florent Kermarrec	79dbb6da4b	replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows)	2015-01-19 09:45:34 +01:00