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1273 commits 42 branches 14 tags 31 MiB
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13 commits

Author SHA1 Message Date
Florent Kermarrec
69764f2e22 global: pep8 (E401) 2015-04-13 20:54:19 +02:00
Florent Kermarrec
37ef9b6f3a global: pep8 (E231) 2015-04-13 20:50:03 +02:00
Florent Kermarrec
1051878f4c global: pep8 (E302) 2015-04-13 20:45:35 +02:00
Florent Kermarrec
17e5249be0 global: pep8 (replace tabs with spaces) 2015-04-13 20:07:07 +02:00
Sebastien Bourdeauducq
e1702c422c introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
Florent Kermarrec
ec080479da mibuild/sim: use the same architecture we use for others backends 2015-03-27 14:14:49 +01:00
Florent Kermarrec
00e8616de2 mibuild/sim: clean up (thanks sb) 2015-03-10 16:41:52 +01:00
Florent Kermarrec
70a3e8081c mibuild/sim: add support for pty 2015-03-09 23:31:11 +01:00
Florent Kermarrec
a72c091bc2 mibuild/sim: regroup console_tb/ethernet_tb in dut_tb 2015-03-09 14:40:31 +01:00
Florent Kermarrec
0029b87628 mibuild/sim: add ethernet pins to verilor.py 2015-03-06 12:20:17 +01:00
Florent Kermarrec
991572f4fe mibuild/sim: create server.py and server_tb (Proof of concept OK with flterm) 
Using a server allow us to create a virtual UART (and ethernet TAP in the future).

1) start the server
2) start flterm on the virtual serial port created by the server
3) run the simulation

This will enable us to do serialboot and netboot in simulation.
This will also enable prototyping  ethernet for ARTIQ in simulation.
 2015-03-03 17:38:22 +01:00
Florent Kermarrec
29c5bb8bcd mibuild/sim/verilator: remove verilator_root, use -Wno-fatal and add verbose option (verbose disabled by default) 2015-03-02 23:23:23 +01:00
Florent Kermarrec
382ca374c3 mibuild: initial Verilator support 2015-03-01 18:27:46 +01:00