10 commits

Author	SHA1	Message	Date
Yann Sionneau	cf92821fcf	Refactor directory hierarchy of sdram phys and controllers	2014-11-27 22:09:10 +08:00
Florent Kermarrec	34ed315a48	remove trailing whitespaces	2014-10-17 17:14:40 +08:00
Sebastien Bourdeauducq	36434b62f0	sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE	2014-09-03 15:02:38 +08:00
Sebastien Bourdeauducq	a7b4550e59	sdramphy/initsequence: cleanup and expose DDR3 MR1 value	2014-09-03 14:21:30 +08:00
Florent Kermarrec	114890ee80	sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT	2014-09-02 10:54:29 +08:00
Florent Kermarrec	85b29c883a	sdramphy/initsequence: fix and add format_mr0 function	2014-08-14 14:17:54 +08:00
Florent Kermarrec	293ac09673	sdramphy/bios: make sdrrd/sdrwr generic	2014-08-08 19:25:10 +08:00
Sebastien Bourdeauducq	cfc37a3fa5	sdramphy/initsequence: rewrite DDR3 initialization sequence	2014-08-08 19:15:05 +08:00
Florent Kermarrec	25b3aff6f1	sdramphy: add init sequence for DDR3	2014-07-31 10:29:32 +08:00
Florent Kermarrec	1adceb8276	sdramphy: move and clean up s6ddrphy, add generic SDRAM PHY	2014-04-17 19:38:25 +02:00

Renamed from misoclib/s6ddrphy/initsequence.py (Browse further)