Sebastien Bourdeauducq
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b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
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f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
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2012-02-17 11:04:44 +01:00 |
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Sebastien Bourdeauducq
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204452b0d3
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m1crg: make clock feedback pin bidirectional
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2012-02-16 18:35:44 +01:00 |
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Sebastien Bourdeauducq
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72f9af9d90
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Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |