5 commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	b4e041ecf1	s6ddrphy: write path OK in simulation	2012-02-20 23:55:20 +01:00
Sebastien Bourdeauducq	f35cd4a85b	Prepare for new DDR PHY	2012-02-19 18:43:42 +01:00
Sebastien Bourdeauducq	5d1dad583b	Connect DDR PHY ... Doesn't do much for the moment, just to check synthesis/P&R.	2012-02-17 11:04:44 +01:00
Sebastien Bourdeauducq	204452b0d3	m1crg: make clock feedback pin bidirectional	2012-02-16 18:35:44 +01:00
Sebastien Bourdeauducq	72f9af9d90	Generate all clocks for the DDR PHY	2012-02-16 18:02:37 +01:00