3 commits

Author	SHA1	Message	Date
Florent Kermarrec	bd4d3cd73b	uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)	2015-03-01 12:14:34 +01:00
Florent Kermarrec	6107b7844a	test implementation on all targets and fix issues	2015-02-28 12:04:51 +01:00
Florent Kermarrec	8564b7eb6a	soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)	2015-02-28 11:44:14 +01:00