4 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	6664af73d1	uart: new design using FHDL and bank (TX only, incomplete)	2011-12-18 00:29:37 +01:00
Sebastien Bourdeauducq	bb21f7584a	32-device, 8-bit CSR bus	2011-12-17 15:54:42 +01:00
Sebastien Bourdeauducq	411e1af980	Proper reset generation	2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq	b487e99bcf	Initial import	2011-12-13 17:33:12 +01:00