7 commits

Author	SHA1	Message	Date
Florent Kermarrec	ff0c8e3d22	add PacketBuffer, simplify architecture and reduce ressource usage	2015-01-22 00:13:19 +01:00
Florent Kermarrec	2bb9c6b649	add verilog backend to use the core with a "standard" flow	2015-01-19 20:38:48 +01:00
Florent Kermarrec	d84ae7c80c	clean up	2015-01-19 18:13:43 +01:00
Florent Kermarrec	6de7e15a0c	refactor code	2015-01-17 13:22:52 +01:00
Florent Kermarrec	6f2c7a236c	add support of identify device command	2015-01-17 02:35:25 +01:00
Florent Kermarrec	175618bcb4	use csr_data_width of 32 to speed up data mila upload	2015-01-16 20:57:01 +01:00
Florent Kermarrec	083bd54121	global clean up ... - remove initial sims - remove SATAPHYDeviceCtrl - rename to LiteSATA - rename test to bist	2015-01-16 20:26:15 +01:00

Renamed from targets/test.py (Browse further)