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Dolu1990-patch-1

Dolu1990-patch-2

Dolu1990-patch-3

allows_clk_name_override

ci-cpus

ci-cva6

ci-dev-test

ci-openrisc

ctu-can-fd

dma_nax

efinix_fixes

efinix_fixes2

efinix_iface_signal_names

export_csr_c_rework

framebuffer_change

generic_toolchain

ghdl_fix

gowin_emcu_uart

hyperbus_2x

hyperbus_io_regs

hyperbus_variable_latency

hyperram_decoupling

hyperram_new

kianv

liteeth_wishbone_tx_rx_buses

master

multi-channel-pwm

naxriscv-merge

naxriscv_update

neorv32_litex_wrapper

neorv32_params

urv

usb_ohci_phy_fix

verilog_improvements

verilog_improvements_2

vexriscv_smp_irqs

video_framebuffer_skip_first_frame

video_mod_fix

wishbone_dma_ctrl

wishbone_word_byte_addressing

wuff

zynqmp_aximaster_eth_i2c_uart

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4ded509444

Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix Gwenhael Goavec-Merou 2024-08-27 09:50:04 +0200
f8feb8a192

Merge pull request #2048 from trabucayre/colognechip_improve Gwenhael Goavec-Merou 2024-08-27 09:49:15 +0200
6d46a5ba05 efinix: Fix PLL with external clock input ifacewriter Dolu1990 2024-08-27 09:02:58 +0200
0fcc27f58f build/colognechip/colognechip.py: simplify constrains file with the new toolchain Gwenhael Goavec-Merou 2024-08-24 12:20:19 +0200
07e11858c6 soc/cores/clock/colognechip.py: rework/fix locked signal Gwenhael Goavec-Merou 2024-08-24 12:19:34 +0200
ef775e0b8e

Merge pull request #2043 from pepijndevos/moreapicula Gwenhael Goavec-Merou 2024-08-24 10:37:17 +0200
ac871c690c Merge remote-tracking branch 'origin/master' into feature/mode_based_bus_crossbar Justin Berger 2024-08-23 16:42:23 -0600
0be8d98154 Add timeout to wb crossbar Justin Berger 2024-08-23 16:38:25 -0600
c857f7845e soc/cores/hyperbus/HyperRAMPHY: Add specific sampling clk_domain. hyperram_decoupling Florent Kermarrec 2024-08-22 19:53:45 +0200
c09d57d52d soc/cores/hyperbus: Minor cleanups. Florent Kermarrec 2024-08-22 17:36:47 +0200
3213cf8f84 soc/cores/hyperbus: Generate shift signal from HyperRAMPHY. Florent Kermarrec 2024-08-22 17:20:54 +0200
0edcd2da0e soc/cores/hyperbus: Cleanup Shift-Register and rename signals. Florent Kermarrec 2024-08-22 17:07:06 +0200
2dd7e3b9b3 soc/cores/hyperbus: Shorten reg signals and use common done for read/write register accesses. Florent Kermarrec 2024-08-22 16:39:30 +0200
19f47aa317 soc/cores/hyperbus: Directly drive phy.cs. Florent Kermarrec 2024-08-22 16:31:52 +0200
120715a3d1 soc/cores/hyperbus: Cleanup parameters. Florent Kermarrec 2024-08-22 16:23:03 +0200
b9210e7553 soc/cores/hyperbus: Also move ClkGen to HyperRAMPHY. Florent Kermarrec 2024-08-22 16:03:55 +0200
4400fbb966 Apicula: add GWINR-18 aliases Pepijn de Vos 2024-08-22 16:02:41 +0200
4f0efc2b25 soc/cores/hyperbus: Add HyperRAMPHY and move related logic to it. Florent Kermarrec 2024-08-22 15:16:33 +0200
f54ecfa5ff soc/cores/hyperbus: Avoid setting sr directly in FSM, use sr_load/sr_load_value. Florent Kermarrec 2024-08-22 14:49:55 +0200
6d0ae25d65

Merge pull request #2046 from enjoy-digital/hyperbus_2x enjoy-digital 2024-08-21 19:25:41 +0200
a88cee70c8 test/test_hyperbus: Update. hyperbus_2x Florent Kermarrec 2024-08-21 17:10:44 +0200
37823e34b6 soc/cores/hyperbus: Simplify Clk Generation. Florent Kermarrec 2024-08-21 17:10:36 +0200
ecd9eee5a4 soc/core/hyperbus: Report Clk Ratio on Status register and use it in software to configure latency. Florent Kermarrec 2024-08-21 15:35:21 +0200
5587f5954d test/test_hyperbus: Add 2:1 test. Florent Kermarrec 2024-08-21 15:00:11 +0200
d22669cf05 soc/cores/hyperbus: Handle 4:1/2:1 specific cases separately, default to 4:1 mode (as before). Florent Kermarrec 2024-08-21 12:07:55 +0200
f6de6e755e soc/cores/hyperbus: Add cd_io/sync_io. Florent Kermarrec 2024-08-21 11:50:46 +0200
43879b0f73 soc/cores/hyperbus: Add clk_ratio support to support x1/x2. Florent Kermarrec 2024-08-21 11:41:13 +0200
22afa34a64 soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions. Florent Kermarrec 2024-08-21 11:17:55 +0200
50f0a1057c soc/cores/hyperbus: Do some tests with sys_2x, seems working. Florent Kermarrec 2024-08-21 10:57:36 +0200
0b028d3956 soc/cores/hyperbus: Add comment to allow switching to SDRTristate. Florent Kermarrec 2024-08-20 22:05:38 +0200
60f83b71fa soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided). Florent Kermarrec 2024-08-20 21:54:15 +0200
298a004f08

Merge pull request #2045 from enjoy-digital/hyperbus_io_regs enjoy-digital 2024-08-20 19:47:01 +0200
3a37d3ba98 software/libbase/hyperram: Add missing #ifdef. hyperbus_io_regs Florent Kermarrec 2024-08-20 17:11:02 +0200
eb29b40e07 soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg. Florent Kermarrec 2024-08-20 16:19:15 +0200
1998c74549 soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg. Florent Kermarrec 2024-08-20 15:44:37 +0200
8b86b16077 soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed). Florent Kermarrec 2024-08-20 15:26:26 +0200
76cf004913 test/test_hyperbus: Update. Florent Kermarrec 2024-08-20 15:17:36 +0200
b0026937c1 soc/software/libbase: Move HyperRAM init code to libbase/hyperram.c. Florent Kermarrec 2024-08-20 14:58:51 +0200
a30651e44e soc/cores/hyperbus: Avoid waiting for clk_phase in IDLE state to reduce latency. Florent Kermarrec 2024-08-20 14:44:33 +0200
b7605bc633

Merge pull request #2044 from VOGL-electronic/json2dts_zephyr_omit_disabled_handler enjoy-digital 2024-08-20 14:29:35 +0200
bfe000150c soc/cores/hyperbus: Rework Clk generation to allow having using an IO Reg. Florent Kermarrec 2024-08-20 14:25:23 +0200
7b413352c2 soc/cores/hyperbus: Directly specify default sys_clk_freq in __init__. Florent Kermarrec 2024-08-20 12:04:23 +0200
8f5c2dfbca soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it). Florent Kermarrec 2024-08-20 12:03:40 +0200
3a53a92bb2 soc/cores/hyperbus: Simplify/Rework Data Shift-Out Register. Florent Kermarrec 2024-08-20 11:34:14 +0200
9c1958d692 soc/cores/hyperbus: Simplify/Rework Data Shift-In Register. Florent Kermarrec 2024-08-20 11:26:58 +0200
c1403db407

json2dts_zephyr: omit disable handler Fin Maaß 2024-08-20 11:13:26 +0200
db86ec08b8 soc/cores/hyperbus: Better split parameters/signals and use intermediate dq_o/oe/i and rwds_o/oe/i signals. Florent Kermarrec 2024-08-20 11:12:17 +0200
1f71f3d68b soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments. Florent Kermarrec 2024-08-20 10:40:24 +0200
a960dc33bc soc/cores/hyperbus: Minor cleanup changes. Florent Kermarrec 2024-08-20 10:26:34 +0200
b95b66b554 soc/cores/hyperbus: Switch to Tristate instead of TSTriple and prepare for SDRTristate (not enabled for now). Florent Kermarrec 2024-08-20 10:10:53 +0200
c5416f1680 fixes for apicula support Pepijn de Vos 2024-08-19 19:54:26 +0200
afc66fd5cf cores/picorv32: Fix idbus.sel for reads. Florent Kermarrec 2024-08-19 13:34:50 +0200
bccd1e9c54 CHANGES.md: Update. Florent Kermarrec 2024-08-19 10:37:13 +0200
6623a5b691

Merge pull request #2028 from VOGL-electronic/spi_ram_add Gwenhael Goavec-Merou 2024-08-16 19:08:48 +0200
26e7eef3ce

Merge pull request #2042 from pepijndevos/apicula Gwenhael Goavec-Merou 2024-08-16 18:58:04 +0200
039be2a248 add dual use gpio options Pepijn de Vos 2024-08-16 15:56:24 +0200
cbb1adfa7b

Merge pull request #2036 from Mai-Lapyst/gowin-add-apicula Gwenhael Goavec-Merou 2024-08-15 08:54:40 +0200
dc3f2d6421

Add missing license header to apicula.py Mai-Lapyst 2024-08-15 01:54:31 +0200
623536cd6a

Remove empty build_timing_constraints override in GowinApiculaToolchain Mai-Lapyst 2024-08-15 01:52:22 +0200
e0968b3574

Adds apicula toolchain to gowin platform Mai-Lapyst 2024-08-12 06:47:57 +0200
b279fc9fb3

Merge pull request #2035 from Mai-Lapyst/fix_empty_initpy Gwenhael Goavec-Merou 2024-08-11 10:06:09 +0200
3d0fe4ebca

Fix litex.build.gowin's __init__.py; closes #2034 Mai-Lapyst 2024-08-11 03:37:41 +0200
6309f30e0b

Merge pull request #2030 from trabucayre/gowin_build_gw5a_primitives enjoy-digital 2024-08-07 09:23:21 +0200
6e0d90667c Documentation Updates BushraArshad96 2024-08-06 16:55:27 +0200
cb6e28aaa2 Merge remote-tracking branch 'origin/master' into vexiiriscv Dolu1990 2024-08-05 09:07:39 +0200
3cd820974a build/gowin/common.py: re-add tristate impl and SDRxxx for GW5A/Arora family (required for SDRAM use) Gwenhael Goavec-Merou 2024-08-04 09:38:52 +0200
cd457c9809 soc: add l2 cache to spi_ram Fin Maaß 2024-07-02 10:50:34 +0200
e29dc39377 openocd/jtagspi: Allow users to specify additional init commands Matthias Breithaupt 2024-06-05 10:44:30 +0200
41b346d141 bios: mem_read: reduce number of reads on mapped registers (only supports 32-bit aligned addresses) Matthias Breithaupt 2024-06-04 10:45:01 +0200
03a0a6fd9b soc: add add_spi_ram function Matthias Breithaupt 2024-05-24 11:57:53 +0000
f855417afc README.md: Be more positive and shorter in moral precisions :). Florent Kermarrec 2024-07-31 14:55:10 +0200
74127d51c5

Merge pull request #2024 from trabucayre/altera_agilex5_sdrtristate_special enjoy-digital 2024-07-30 19:22:25 +0200
1f6673c6eb build/altera/common.py: implement SDRTristate for Agilex5 family Gwenhael Goavec-Merou 2024-07-30 16:32:54 +0200
cd3364a433 litex/gen/verilog: use format_constant Andrew Dennison 2024-03-04 01:18:28 +0000
12e1f3f4da litex/soc/integration: use format_constant for soc.h Andrew Dennison 2024-03-03 23:17:06 +0000
51a6914afa litex/gen: add format_constant Andrew Dennison 2024-03-04 01:14:29 +0000
222848298f software/bios: add target hooks Andrew Dennison 2024-02-29 12:41:28 +1100
93a7cc2523 cmd_bios.c: Fix wrong byte size of uptime in uptime_handler. Denis Ryndine 2024-02-13 21:56:06 +0000
dbc1f665f7 software/bios/boot: fix warnings Andrew Dennison 2024-02-07 17:26:23 +1100
6f0b39772a litex/tools: Add RemoteI2C Andrew Dennison 2024-03-10 18:00:24 +1100
715098f2f1 soc/cores/i2c: add dts support Andrew Dennison 2024-07-22 12:23:47 +1000
e7111a5ee3 soc/cores/gpio: add dts support Andrew Dennison 2024-07-10 12:36:37 +1000
c112f068d1 soc/cores/spi/spi_mmap: add dts support Andrew Dennison 2024-07-10 12:36:37 +1000
03751815da soc/cores/timer: add dts support Andrew Dennison 2024-07-10 12:36:37 +1000
84e936dbc9 Pass DTS information from modules to json2dts Andrew Dennison 2024-07-10 12:35:44 +1000
362e2cbcb1 soc/integration/builder: exclude dts constants Andrew Dennison 2024-05-28 10:41:31 +1000
1b839d0641 tools/litex_json2dts_linux: add soc, csr, mem helpers Andrew Dennison 2024-05-27 16:47:44 +1000
e19dfa8800 tools/litex_json2dts_zephyr: fix reg format Andrew Dennison 2024-05-27 17:03:45 +1000
2776b63d1a tools/litex_json2dts_zephyr: improve indentation Andrew Dennison 2024-05-24 12:05:28 +1000
3041150773

Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special enjoy-digital 2024-07-26 18:26:19 +0200
ba8830e6cd global: Remove @trabucayre's tracers :) Florent Kermarrec 2024-07-26 12:56:50 +0200
5c5bc82f22 interconnect/packet/PacketFIFO: Fix payload_fifo.sink.valid. Florent Kermarrec 2024-07-26 11:52:17 +0200
dc04949d78 build/altera/common,platform: added ddrinput/ddrout primitives Gwenhael Goavec-Merou 2024-07-25 14:11:06 +0200
531cf82bdd add crt0.o to BIOS target list hhe07 2024-07-22 20:13:47 -0600
c51d22074f soc/integration/soc/add_uart: Allow directly passing uart_pads. Florent Kermarrec 2024-07-22 16:22:29 +0200
b8cb6da2b9 soc/cores/clock/lattice_nx.py: added clk contraints for OSCA output Gwenhael Goavec-Merou 2024-07-22 15:11:40 +0200
ecd0f0e548 cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K. Florent Kermarrec 2024-07-22 14:24:34 +0200
4662b95f16

Merge pull request #2012 from machdyne/master enjoy-digital 2024-07-21 09:34:00 +0200
4301293b21

Merge pull request #2018 from motec-research/add_i2c_master enjoy-digital 2024-07-21 09:32:48 +0200
67e6614eb2 test_i2c: whitespace cleanups Andrew Dennison 2023-09-04 11:16:49 +1000