Florent Kermarrec aab8912f5a soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU.		2024-10-17 17:44:40 +02:00
..
build	build: efinix: use ifacewriter to set bank voltage	2024-10-08 09:05:04 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU.	2024-10-17 17:44:40 +02:00
tools	Merge pull request #1974 from motec-research/dts_zephyr_updates	2024-09-17 14:58:51 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00