Sebastien Bourdeauducq 0999a17319 verilog, sim: accept iterables in FHDL statements		2015-10-19 19:17:26 +08:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
bitcontainer.py	fhdl: replace flen with len	2015-09-26 18:45:10 +08:00
conv_output.py	introduce conversion output object (prevents file IO in FHDL backends)	2015-04-08 20:28:23 +08:00
decorators.py	fhdl/decorators: remove traces of deprecated API	2015-09-12 19:44:35 +08:00
edif.py	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
module.py	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
namer.py	fhdl/namer: support ClockSignal and ResetSignal. Closes #24	2015-09-22 14:30:16 +08:00
simplify.py	fhdl/FullMemoryWE: fix clocking	2015-09-29 13:12:27 +08:00
specials.py	fhdl/specials/Tristate: handle i=None	2015-09-26 21:49:12 +08:00
structure.py	fhdl: typecheck ClockSignal and ResetSignal arguments	2015-09-29 13:11:40 +08:00
tools.py	fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem	2015-09-15 12:38:02 +08:00
tracer.py	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
verilog.py	verilog, sim: accept iterables in FHDL statements	2015-10-19 19:17:26 +08:00
visit.py	fhdl/visit: support Constant	2015-09-20 16:10:17 +08:00