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304 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 0999a17319 verilog, sim: accept iterables in FHDL statements 2015-10-19 19:17:26 +08:00
Sebastien Bourdeauducq 6d2d70d879 fhdl/FullMemoryWE: fix clocking 2015-09-29 13:12:27 +08:00
Sebastien Bourdeauducq b4c5ffc1ba fhdl: typecheck ClockSignal and ResetSignal arguments 2015-09-29 13:11:40 +08:00
Sebastien Bourdeauducq 09003a55e1 fhdl/specials/Tristate: handle i=None 2015-09-26 21:49:12 +08:00
Sebastien Bourdeauducq e136352e8f fhdl/structure: relax type requirements for Array elements 2015-09-26 21:47:33 +08:00
Sebastien Bourdeauducq 808cf06add fhdl: replace flen with len 2015-09-26 18:45:10 +08:00
Sebastien Bourdeauducq fa1e8cd822 wrap expressions in Specials 2015-09-26 16:45:13 +08:00
Sebastien Bourdeauducq 8f42b6f352 fhdl: introduce wrap function 2015-09-26 15:36:28 +08:00
Sebastien Bourdeauducq 67903494bf fhdl: export DUID 2015-09-26 13:46:57 +08:00
Sebastien Bourdeauducq 1857ec6c32 fhdl/namer: support ClockSignal and ResetSignal. Closes #24 2015-09-22 14:30:16 +08:00
Sebastien Bourdeauducq 34ce6b077f verilog: remove unneeded import 2015-09-21 21:19:58 +08:00
Sebastien Bourdeauducq 1767eef9cb fhdl/visit: support Constant 2015-09-20 16:10:17 +08:00
Sebastien Bourdeauducq 320dffb4ac sim: memory access from generators 2015-09-20 14:52:26 +08:00
Sebastien Bourdeauducq 59802bec76 fhdl/structure: add missing init 2015-09-20 14:46:30 +08:00
Sebastien Bourdeauducq 1861ae9d01 fhdl/specials: MemoryPort.clock should always be a ClockSignal 2015-09-19 23:21:24 +08:00
Sebastien Bourdeauducq 262fd50677 fhdl/simplify: add MemoryToArray 2015-09-19 23:20:57 +08:00
Sebastien Bourdeauducq 776579f0d7 fhdl/structure: all case statements should be lists 2015-09-17 17:22:24 +08:00
Sebastien Bourdeauducq bcf62997f6 fhdl/bitcontainer: remove fiter 2015-09-17 17:22:03 +08:00
Sebastien Bourdeauducq c2109f8f81 minor bugfixes 2015-09-17 15:20:27 +08:00
Sebastien Bourdeauducq 9dd3200ba2 fhdl/structure: fix namespace pollution 2015-09-17 14:39:17 +08:00
Sebastien Bourdeauducq 0a92e346d3 fhdl/bitcontainer: remove fslice and freversed 2015-09-17 14:38:33 +08:00
Sebastien Bourdeauducq f5ab734bdf fhdl/verilog: fix case value sort 2015-09-17 08:03:48 +08:00
Sebastien Bourdeauducq e940c6d9b9 fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem 2015-09-15 12:38:02 +08:00
Sebastien Bourdeauducq 42afba2bbc fhdl/decorators: remove traces of deprecated API 2015-09-12 19:44:35 +08:00
Sebastien Bourdeauducq 1bdb9bee22 fhdl/decorators: remove deprecated API 2015-09-12 19:34:44 +08:00
Sebastien Bourdeauducq 336728413a simplify imports, migen.fhdl.std -> migen 2015-09-12 19:34:07 +08:00
Sebastien Bourdeauducq 49ef182305 fhdl/tools: add input lister 2015-09-10 20:33:10 -07:00
Sebastien Bourdeauducq f9849fb8be style 2015-09-10 20:32:47 -07:00
Sebastien Bourdeauducq 714ae43ab8 fhdl: remove features new simulator won't use 2015-09-10 18:29:57 -07:00
Yves Delley 1dcd2ac1c0 fixed bug in value_bits_sign of mul operatiors 2015-09-10 10:53:26 -07:00
Sebastien Bourdeauducq f32f9be17a resetless -> reset_less 2015-07-27 11:46:11 +08:00
Sebastien Bourdeauducq cc6877df9e fhdl: allow use of ResetSignal() on resetless clock domains 2015-07-27 01:51:52 +08:00
Florent Kermarrec 1f1ff5a5e9 migen/fhdl/tools: fix rename_clock_domain when new == old 
Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
 2015-07-24 12:48:51 +02:00
Florent Kermarrec d77a5fc5ac fhdl/specials: add Keep SynthesisDirective 2015-06-23 16:14:42 +02:00
Florent Kermarrec a5f495aeac fhdl/verilog: add reserved keywords 2015-05-23 14:01:08 +02:00
Florent Kermarrec 67702f25ab migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb) 2015-04-24 12:54:08 +02:00
Florent Kermarrec bc30fc57e7 migen/fhdl: give explicit names to syntax specialization when asic_syntax is used 2015-04-24 12:14:14 +02:00
Guy Hutchison 28dde1e38f fhdl/verilog: add flag to produce ASIC-friendly output 2015-04-21 09:52:14 +08:00
Florent Kermarrec 3f15699964 revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue) 2015-04-13 21:47:55 +02:00
Florent Kermarrec f97d7ff44c global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
Florent Kermarrec 37ef9b6f3a global: pep8 (E231) 2015-04-13 20:50:03 +02:00
Florent Kermarrec 1051878f4c global: pep8 (E302) 2015-04-13 20:45:35 +02:00
Florent Kermarrec 17e5249be0 global: pep8 (replace tabs with spaces) 2015-04-13 20:07:07 +02:00
Florent Kermarrec ff23960657 fhdl/verilog: avoid reg initialization in printheader when reset is not an int. 
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
 2015-04-10 17:18:07 +02:00
Sebastien Bourdeauducq e1702c422c introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
Robert Jordens 8798ee8d73 decorators: fix stacklevel, export in std 2015-04-05 18:47:45 +08:00
Robert Jordens f26ad97624 decorators: fix ControlInserter 2015-04-05 14:44:03 +08:00
Sebastien Bourdeauducq db76defa2a fhdl/visit: remove TransformModule 2015-04-04 20:12:22 +08:00
Robert Jordens e702fb7727 decorators: fix class/instance logic 2015-04-04 19:16:58 +08:00
Robert Jordens 4091af69fd fhdl/decorators: make the transform logic more idiomatic 
* the transformers work on classes and instances.
  you can now do just do:

    @ResetInserter()
    @ClockDomainRenamer({"sys": "new"})
    class Foo(Module):
        pass

  or:

    a = ResetInserter()(FooModule())

* the old usage semantics still work
* the old DecorateModule is deprecated,
  ModuleDecorator has been refactored into ModuleTransformer
  (because it not only decorates things)
 2015-04-04 19:16:50 +08:00